The reports about an inadequate supply of calculate GPUs utilized for expert system (AI) and high-performance computing (HPC) servers ended up being typical in current months as need for GPUs to power generative AI applications blew up. TSMC confesses that the most significant calculate GPU supply traffic jam is its chip-on-wafer-on-substrate (CoWoS) product packaging capability, as it is utilized by essentially everybody in the AI and HPC company. The business is broadening CoWoS capability however thinks that its scarcity will continue for 1.5 years.
“ It is not the scarcity of AI chips,” stated Mark Liu, the chairman of TSMC, in a discussion with Nikkei. “ It is the scarcity of our CoWoS capability. [â¦] Presently, we can not meet 100% of our clients’ requirements, however we attempt to support about 80%. We believe this is a short-term phenomenon. After our growth of [advanced chip packaging capacity], it must be minimized in one and a half years.“
TSMC presently produces the large bulk of processors that power popular AI services, consisting of calculate GPUs (such as AMD’s Impulse MI250 and NVIDIA’s A100 and H100), FPGAs, and specialized ASICs from business like d-Matrix and Tenstorrent in addition to exclusive processors from cloud provider, such as AWS’s Trainium and Inferentia in addition to Google’s TPU.
It is notable that calculate GPUs, FPGAs, and accelerators from CSPs all utilize HBM memory to get the greatest bandwidth possible and utilize TSMC’s interposer-based chip-on-wafer-on-substrate product packaging. While standard outsourced semiconductor assembly and test ( OSAT) business like ASE and Amkor likewise provide comparable product packaging innovations, it appears like TSMC is getting the lion’s share of the orders, which is why it can hardly fulfill need for its product packaging services.
Market experts think that OSATs are less encouraged to provide innovative product packaging services due to the fact that it needs them to invest significant quantities of capital and postures more monetary dangers than standard product packaging. For instance, if something fails with a mainstream processor that rests on a natural substrate, an OSAT loses just one chip, whereas if something fails with a plan bring 4 chiplets and 8 HBM memory stacks, the business loses hundreds if not countless dollars. Because OSATs do not get significant margins making those chiplets, such dangers decrease the growth of innovative product packaging capability at OSATs, although innovative product packaging expenses substantially more cash than standard product packaging.
Similar to its market peers, TSMC is investing billions on upcoming innovative product packaging centers. For instance, the business just recently revealed strategies to s pend almost $2.9 billion on a product packaging fab that is reported to come online in 2027.
“ We are increasing our capability as rapidly as possible,” stated C.C. Wei, president of TSMC, at the business’s revenues call previously this year. “ We anticipate these tightness rather be launched in next year, most likely towards completion of next year. [â¦] I will not offer you the specific number [in terms of processed wafers capacity], however CoWoS [capacity will be doubled in 2024 vs. 2023].“
Source: Nikkei